-------------------------------------------------------------------------------
-- Description: This is the testbench that instantiates the arithmetic unit and provides
-- the input signals. The outputs can be checked on the simulation waveforms.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity tb_controler is
end tb_controler;

architecture structural of tb_controler is
	component ALU_contoler
		port(clk     : in  std_logic;
			 rst     : in  std_logic;
			 BTN0    : in  std_logic;
			 RegCtrl : out STD_LOGIC_VECTOR(1 downto 0);
			 FN      : out STD_LOGIC_VECTOR(2 downto 0)
		);
	end component ALU_contoler;

	component CLOCKGENERATOR
		generic(clkhalfperiod : time);
		port(
			clk : out std_logic
		);
	end component;
	signal BTN0    : std_logic;
	signal rst     : std_logic;
	signal RegCtrl : std_logic_vector(1 downto 0);
	signal FN      : std_logic_vector(2 downto 0);
	signal clk     : std_logic;

	constant period : time := 25 ns;

begin                                   -- structural


	BTN0 <= '0',                        -- Pass A
		'0' after 1 * period,           -- Pass B
		'0' after 2 * period,           -- Pass A
		'1' after 3 * period,           -- Pass B
		'1' after 4 * period,           -- Pass A + B
		'1' after 5 * period,           -- Pass A - B  
		'0' after 6 * period,           -- Pass A - B
		'1' after 7 * period,           -- Pass A + B
		'0' after 8 * period,           -- Pass A - B
		'1' after 9 * period, '0' after 10 * period, '1' after 11 * period, '0' after 12 * period, '1' after 13 * period, '0' after 14 * period, '1' after 15 * period, '0' after 16 * period;

	rst <= '0' after 17 * period;

	CLOCKGEN : clockgenerator
		generic map(clkhalfperiod => 2500 ps)
		port map(clk => clk);

	DUT : ALU_contoler
		port map(
			clk     => clk,
			rst     => rst,
			BTN0    => BTN0,
			RegCtrl => RegCtrl,
			FN      => FN
		);

end structural;
